Operating systems use processor paging to isolate the address space of its processes and to efficiently utilize physical memory. Paging is the process of converting a process-specific linear address to a system physical address. When a processor is in paged mode, which is the case for modern operating systems, paging is involved in every data and instruction access. x86 processors utilize various hardware facilities to reduce overheads associated with paging. However, under virtualization, where the guest’s view of physical memory is different from system’s view of physical memory, a second level of address translation is required to convert guest physical addresses to machine addresses. To enable this additional level of translation, the hypervisor must virtualize processor paging. Current software-based paging virtualization techniques such as shadow-paging incur significant overheads, which result in reduced virtualized performance, increased CPU utilization and increased memory consumption. Continuing the leadership in virtualization architecture and performance, AMD64 Quad-Core processors are the first x86 processors to introduce hardware support for a second or nested level of address translation. This feature is a component of AMD Virtualization technology (AMD-V™) and referred to as Rapid Virtualization Indexing (RVI) or nested paging. Under nested paging, the processor utilizes nested page tables, which are set up by the hypervisor, to perform a second level address translation. Nested Paging reduces the overheads found in equivalent shadow paging implementations.
This whitepaper discusses the existing software-based paging virtualization solutions and their associated performance overheads. It then introduces AMD-V™ Rapid Virtualization Indexing technology – referred to as nested paging within this publication – highlights its advantages and demonstrates the performance uplift that may be seen with nested paging.